When accessing a real memory or a real I/O unit, a general-purpose processor transmits an address signal, control signals including a read instruction and a write instruction, and data in the case of a write instruction, to a peripheral LSI generally called a companion chip. A general-purpose processor means a processor manufactured as a general-purpose product with no correction made for a specific application, that can be obtained in a commercial market, among processors that are manufactured by semiconductor makers as microprocessors in general. Examples of the general-purpose processors are the Pentium processor manufactured by Intel, the VR5000 processor manufactured by NEC, and the SH3 processor manufactured by Hatachi. In the following description, an apparatus that is equipped with such a general-purpose processor and a companion chip will be referred to as a program executing apparatus.
FIG. 9 is a block diagram showing a schematic configuration of a conventional program executing apparatus and a conventional program development supporting apparatus. This figure particularly shows a case in which a program executing apparatus is used as a programmable controller 10, and a program development supporting apparatus is used as a control program development supporting apparatus 20. The programmable controller is also called a programmable logic controller (PLC) or a sequencer, and generally operates according to a description of a special control program for sequence processing.
As shown in FIG. 9, the programmable controller 10 has a general-purpose processor 11, a companion chip 12 and a memory 13. The general-purpose processor 11, companion chip 12 and memory 13 are connected to each other through a system bus 15. This system bus 15 is constructed with an address bus, a data bus, and a control bus.
The sequence processing by the programmable controller 10 is basically performed as follows. That is, a signal is received from an input device, such as different types of sensors or various switches, and a control signal is transmitted to an output device, such as a display or an electromagnetic relay, based on a state of the input signal or in a specific order. The control program is a program that describes a flow of the sequence processing by the input device or the output device (i.e., an external device 30 shown in FIG. 9).
In general, this control program is developed using a general-purpose computer. A general-purpose computer means a personal computer or a program loader (i.e., a control program development supporting apparatus 20 shown in FIG. 9). The developed control program is transferred to the programmable controller through a communication interface. Particularly, the programmable controller 10 shown in FIG. 9 is a compiling programmable controller, which receives and executes an execution code 9 generated by the control program development supporting apparatus 20.
FIG. 10 is a diagram for explaining a process of generating the execution code 9 by the control program development supporting apparatus 20. In the control program development supporting apparatus 20, a conversion tool 101 converts a control program 1 described in a language for sequence processing, such as a ladder diagram or an instruction list, into a general-purpose language program 5. The general-purpose language program 5 is a program written in a programming language which many programmers know and which can be developed and corrected easily. Examples, of such programming languages are the C language and the C++ language. The control program development supporting apparatus 20 then compiles this general-purpose language program 5 using a general-purpose language compiler 102, thereby to generate the execution code 9.
In other words, the control program development supporting apparatus 20 can produce the execution code 9, that can be directly executed in the general-purpose processor 11 of the compiling programmable controller 10, from the control program 1, such as the instruction list.
The companion chip 12 shown in FIG. 9 not only functions as a relay for the general-purpose processor 11 to make access to the memory 13 but also provides, in may cases, an interface with a peripheral unit, such as the external device 30 connected to the outside. It is also possible to download the execution code 9 into the memory 13 through the companion chip 12.
Further, as one of methods for the general-purpose processor 11 to make access to the peripheral unit, such as the external device 30 for carrying out control, there has been known a memory mapped I/O system. The memory mapped I/O system allocates a control register of the peripheral unit to a part of a real memory address space of the memory 13 (hereinafter to be referred to as a physical address space to distinguish this real memory address space from the whole of the memory 13). According to the memory mapped I/O system, the general-purpose processor 11 accesses the control register of the peripheral unit by using a load/store instruction in a similar manner to that of accessing a work memory for carrying out an operation processing.
As another method of controlling a peripheral unit, there has been known an I/O address system that allocates a control register of the peripheral unit to an I/O address space exclusively for the peripheral unit, prepared separately from the physical address space. According to this I/O address system, the general-purpose processor 11 accesses the control register of the peripheral unit by using an exclusive I/O address access instruction, such as an IN instruction or an OUT instruction. The general-purpose processor 11 shown in FIG. 9 employs the I/O address system, and has a physical address space 40 and an I/O address space 50 within the memory 13.
Referring to FIG. 9, for making access to a physical address space 40 and an I/O address space 50, the general-purpose processor 11 transmits either an input command or an output command, and an address for indicating an address of a requested data, to the companion chip 12.
Upon receiving the address, the companion chip 12 extracts the data allocated to the requested address from the physical address space or the I/O address space, using an address conversion function set in advance, and transmits this data to the general-purpose processor 11. In the general-purpose processor 11, the minimum unit of data input/output is one byte (that is, eight bits). The general-purpose processor 11 can read data consisting of one byte, two bytes, four bytes, or eight bytes at once.
FIG. 11 is a diagram for explaining a data array in a physical address space. Furthermore, FIG. 12 is a diagram for explaining a data array in an I/O address space. In the control program 1 of the programmable controller 10, a device having X or Y attached to the header of a name of a variable means a device in the I/O address space. A device having M attached to the header of a name of variable means a device in the physical address space. In FIG. 11, a physical memory means a memory 13, such as a DRAM. In FIG. 12, physical I/O means a control register provided in a peripheral unit, such as the external device 30.
As shown in FIG. 11 and FIG. 12, the physical address space 40 and the I/O address space 50 have addresses identified in byte (eight bits) units. The general-purpose processor 11 makes access to the peripheral unit in byte units as well as carrying out operational processing in byte units.
The processing carried out by the general-purpose processor 11 is broadly divided into three. They are “a read processing for reading data from the outside into the register on the general-purpose processor 11”, “an operational processing for processing data on the register”, and “a write processing for writing data from the register to the outside”. The general-purpose processor 11 achieves various kinds of program processing by repeating these three types of processing.
The general-purpose processor 11 processes data in its register in one clock cycle, based on an input clock. However, it takes a few clock cycles for the general-purpose processor 11 to make data access to and from the outside, that is, for the “processing of reading data from the outside” and the “processing of writing data to the outside”. As a result, there has been a problem because most of the processing time is spent making access to data to and from the outside when a program has a content making frequent external data access. This results in a drop in the speed of executing the processing.
Further, in the programmable controller 10 shown in FIG. 9, many types of processing are carried out in bit units. When it is desired to read only one specific bit data, the general-purpose processor 11 installed in this apparatus must read at least eight bits, as the address access is in byte units in the programmable controller 10 as described above. In this case, the remaining seven bits become useless. Particularly, when it is desired to make access to n bit data that are arrayed in mutually different addresses, it is necessary to read meaningless data of 7×n bits.
The problems mentioned above will be explained in detail through examples. FIG. 13 is a diagram showing one example of a ladder diagram as one mode of the control program 1. The ladder diagram is a graphical programming language used in the programmable controller, and has a programming mode mainly for carrying out a logical operation called a contact (also called a bit device). In general, the ladder diagram has a mode of repetitively carrying out a logical operation like an AND operation and an OR operation to a necessary bit device and carrying out a certain operation when a result of the logical operation is true.
The ladder diagram shown in FIG. 13 expresses a realization of a series of sequence processing by making access to input devices X0, X8 and Xf, memory devices M0 and M10, and output devices Y0 to Y8.
In actual practice, the ladder diagram is converted into a text programming language called an instruction list (IL) that expresses processing equivalent to that of the original ladder diagram. The conversion tool 101 shown in FIG. 10 and an interpreter program controller directly handle this instruction list.
FIG. 14 is an instruction list that equivalently expresses the ladder diagram shown in FIG. 13. In FIG. 14, numbers (1) to (9) are row numbers prepared to facilitate the explanation, and these numbers do not exist in the actual instruction list. The contents of the processing corresponding to each row number will be explained below.    (1) Read a value of the bit X0 into the register of the general-purpose processor 11.    (2) Carry out an AND operation of the loaded data and a value of the bit X8.    (3) Read a value of the bit Xf into the register of the general-purpose processor 11.    (4) Carry out an AND operation of the loaded data and a value of the bit M8.    (5) Carry out an OR operation of the operation result of (2) above and the operation result of (4) above.    (6) Carry out an OR operation of the operation result of (5) above and the bit M0.    (7) Write the operation result of (6) above into the bit Y0.    (8) Write the operation result of (6) above into the bit Y8.    (9) Write the operation result of (6) above into the bit M10.
The control program development supporting apparatus 20 shown in FIG. 1 further needs to convert the instruction list described as shown in FIG. 14 into a general-purpose language program using the conversion tool 101. It is assumed that a general-purpose language program generated by the conversion tool 101 is a program described in the C language, and the general-purpose processor 11 is an eight-bit processor, as an example.
FIG. 15 is a diagram showing a result of converting the instruction list shown in FIG. 14 into an expression in the C language. In FIG. 15, numbers “001:” to “024:” are row numbers that are prepared to facilitate the explanation, and they do not exist in the actual C language source list. The contents of processing for each row are explained below. In order to make clear the correspondence between these processing contents and the instruction list shown in FIG. 14, the row numbers in the instruction list shown in FIG. 14 are called IL row numbers, and the row numbers in the source list described in the C language shown in FIG. 15 are called C row numbers.
Referring to FIG. 15, first in the C row number “001:”, the statement declares that variables r1 to r8 that are used in this source are unsigned eight-bit character data. As described above, the input/output of the data stored in the memory is carried out in byte units. Therefore, in order to realize processing corresponding to the IL row number (1) in the C language, it is necessary to process one-byte data that includes the bit data X0, that is, one byte data stored in an address “a000” in the I/O address space.
Therefore, in the C row number “002:”, the eight-bit data stored in the address “a0000” is substituted into the variable r1.
The processing of the IL row number (2) requires the bit data X8. Therefore, in the C row number “003:”, the data having the address “a001” that includes the bit data X8 is substituted into the variable r2.
In the C row number “004:”, the variabler 2 is substituted into the variable r3 in order to use the variable r3 as a variable that handles the bit data X8 as described later. In other words, at this state, the variable r3 includes the bit data Xf.
In the C row number “005:”, an AND operation of the variable r1 and the variable r2 is carried out in bit units in order to realize the AND operation of the IL row number (2). The result of the AND operation is substituted into the variable r1. In this case, the bit data X0 is positioned at the lowest bit (hereinafter referred to as a zero-order bit) of the data stored in the address “a000”. Similarly, the bit data X8 is also positioned at the zero-order bit of the data stored in the address “a001”. Therefore, the AND operation result of the zero-order bits of the variable r1 and the variable r2 represents the result of the AND operation of the bit data X0 and X8.
The read processing of the bit data Xf is achieved in the IL row number (3). For this purpose, next, in the C row number “006:”, the variable r3 is shifted to the right by seven bits. The shifted result is substituted into the variable r3. The bit data Xf is positioned at the highest bit (hereinafter referred to as a seventh bit) of the address “a001”. Therefore, the bit data Xf is included in the variable r2 that has already been substituted in the C row number “003”, that is, in the variable r3. Thus, when the bit data of the variable r3 is shifted to the right by seven bits, it is possible to obtain one byte in which the bit data Xf is positioned at the zero-order bit. As a result, the variable r3 after the shifting of bits can be utilized as the variable for processing the bit data Xf.
Next, the processing of the IL row number (4) requires the bit data M8. Therefore, in the C row number “007:”, the data having the address “0001” in the physical address space that includes the bit data M8 is substituted into the variable r4.
In the C row number “008:”, an AND operation of the variable r4 and the variable r3 is carried out in bit units in order to realize the AND operation of the IL row number (4). The result of the AND operation is substituted into the variable r4. Thus, the AND operation of the bit data Xf and the bit data M8 is realized by the AND operation of the variable r4 and the zero-order bit of the variable r3.
At this stage, the zero-order bit of the variable r1 expresses the AND result of the IL row number (2), and the zero-order bit of the variable r4 expresses the AND result of the IL row number (4). Therefore, in the C row number “009:”, an OR operation of the value of the variable r1 and the variabler 4 is carried out in bit units in order to realize the OR operation of the IL row number (5). The result of the OR operation is substituted into the variable r1.
Next, the processing of the IL row number (6) requires the bit data M0. Therefore, in the C row number “010:”, the data having the address “0000” in the physical address space that includes the bit data M0 is substituted into the variable r5.
At this stage, the zero-order bit of the variable r1 expresses the AND result of the IL row number (2) and the OR result of the IL row number (4). Therefore, in the C row number “011:”, an OR operation of the variable r1 and the variable r5 is carried out in bit units in order to realize the OR operation of the IL row number (6). A result of the OR operation is substituted into the variable r1.
Next, in the C row number “012:”, an AND operation of the variable r1 and a hexadecimal value “0001” is carried out in bit units in order to maintain the state of only the zero-order bit of the variable r1 and to clear the bit data of the first to seventh bits of the variable r1. The result of the AND operation is substituted into the variable r1.
In the processing of the IL row number (7), data is written into the bit data Y0. Therefore, in the C row number “013:”, the data of the address “a002” in the I/O address space that includes the bit data Y0 is substituted into the variable r6.
Next, in the C row number “014:”, an AND operation of the variable r6 and a hexadecimal value “FFFE” is carried out in bit units in order to maintain the state of only the first to seventh bits of the variable r6 and to clear the zero-order bit of the variable r6. The result of the AND operation is substituted into the variable r6.
At this stage, as shown in the C row number “015:”, an OR operation of the variable r6 and the variable r1 is carried out in bit units. The result of the OR operation is substituted into the variable r6. As a result, the variable r6 becomes a byte in which only the zero-order bit has been replaced by the OR result of the zero-order bit of the IL row number (6).
In the processing of the IL row number (8), data is written into the bit data Y8. Therefore, in the C row number “016:”, the data of the address “a003” in the I/O address space that includes the bit data Y8 is substituted into the variable r7.
Next, in the C row number “017:”, an AND operation of the variable r7 and the hexadecimal value “FFFE” is carried out in bit units in order to maintain the state of only the first to seventh bits of the variable r7 and to clear the zero-order bit of the variable r7. The result of the AND operation is substituted into the variable r7.
At this stage, as shown in the C row number “018:”, an OR operation of the variable r7 and the variable r1 is carried out in bit units. The result of the OR operation is substituted into the variable r7. As a result, the variable r7 becomes a byte in which only the zero-order bit has been substituted by the OR result of the zero-order bit of the IL row number (6).
In the processing of the IL row number (9), data is written into the bit data M10. Therefore, in the C row number “019:”, the data of the address “0002” in the physical address space that includes the bit data M10 is substituted into the variable r8.
Next, in the C row number “020:”, an AND operation of the variable r8 and the hexadecimal value “FFFE” is carried out in bit units in order to maintain the state of only the first to seventh bits of the variable r8 and to clear the zero-order bit of the variable r8. The result of the AND operation is substituted into the variable r8.
At this stage, as shown in the C row number “021:”, an OR operation of the variable r8 and the variable r1 is carried out in bit units. The result of the OR operation is substituted into the variable r8. As a result, the variable r8 becomes a byte in which only the zero-order bit has been replaced by the OR result of the zero-order bit of the IL row number (6).
In the C row number “022:”, the variable r6 obtained by the above operation is actually written into the address “a002” in order to realize the processing of the IL row number (7). Similarly, in the C row number “023:”, the variable r7 obtained by the above operation is actually written into the address “a003” in order to realize the processing of the IL row number (8). In the C row number “024:”, the value r8 obtained by the above operation is actually written into the address “0002” in order to realize the processing of the IL row number (9).
As explained above, it is necessary to carry out the processing in byte units in the source list that is expressed in the C language. Therefore, in order to process the bit data corresponding to each device, it is necessary to carry out data reading seven times in the C row numbers “002:”, “003:”, “007:”, “010:”, “013:”, “016:”, and “019:” and data writing three times in the C row numbers “022:”, “023:” and “024:”. When n clocks are required, where n is larger than 1, for accessing each device, there arises a data transfer waiting time of a total of about 10×n clocks in addition to the time required for the actual logical processing.